Welcome to MicroBenchmark documentation!
Datasheet
- Simple Gates
- Simple Registers
- Finite State Machines
- Processors
- Interface
- CAN Protocol Controller IP Core
- UART IP Core
- SPI Core
- PWM/Timer/Counter IP Core
- I2C-Master Core
- GPIO IP Core
- Wishbone Scope
- Wishbone LCD Controller
- Wishbone LCD Controller RAM-Less
- Wishbone QSPI
- Wishbone RS232 Controller
- wbi2c
- Wishbone 1-Wire Master
- Wishbone SPI Master
- Real-time Clock
- RS485 Interface
- FPGA-liteCAN
- routing_test
- SAP-1 8-Bit Computer (SAPone)
- Test CLB Modes
- UberDDR3
- verilog_spi
- wbspi_master
- wbuart32
- DSP
- Cordic
- Cordic Core
- CR Div
- Signed Integer Divider
- Digital Filters
- N-bit Multiply-Accumulate Circuit (mac_N)
- N-bit Combinatorial Multiplier (mult_NxN)
- Macro-based N-bit Multiplier
- square_32
- PID controller
- N-bit Pipelined Multiplier
- 8-bit Pipelined Multiplier N-Clock
- dual_mult8_mix_regin
- mult8_ram8
- two_mult8_ram32
- Memory
- Synchronous 4x1 Single-Port RAM
- 4x1 Asynchronous Read SPRAM
- Dual-Port RAM 1K (128x8)
- Dual-Port RAM 16K (2048x8)
- Dual-Port RAM 8x16 and 8x32 MIF Single Clock
- Dual-Port RAM 8x32 MIF Single Clock MIF
- dual_port_ram_8x16_mif
- Dual-Port RAM 8x16 MIF N-Clock
- Synchronous FIFO Buffer
- Pipelined 8-Bit Adder with RAM Caching
Developer Guidelines
Appendix