Blinking

Introduction

This benchmark is designed to test the flip-flop/registers in FPGAs. It is a 1-bit clock divider, which outputs half frequency of the input clock.

Source codes

See details in simple_registers/blinking

Block Diagram

Fig. 1 Blinking schematic

Performance

Expect to consume only 1 LUT and 1 flip-flop of an FPGA. It can reflect the maximum speed of an FPGA between a LUT and a flip-flop.

Warning

The following resource utilization is just an estimation! Different tools in different versions may result differently.

Table 1 Estimated resource Utilization

Tool/Resource	Inputs	Outputs	LUT4	FF	Carry	DSP	BRAM
General	0	1	1	1	0	0	0