Clock Divider

Introduction

This benchmark is designed to test the flip-flop/registers in FPGAs. The benchmark takes an input clock signal clk_i and generates an output clock signal clk_o with one fourth the frequency of the input clock. The module also has a reset input rst to reset output signals.

Source codes

See details in simple_registers/clk_divider

Block Diagram

Fig. 2 Clock divider schematic

Performance

Expect to consume only 2 LUT and 2 flip-flop of an FPGA. It can reflect the maximum speed of an FPGA between a LUT and a flip-flop.

Warning

The following resource utilization is just an estimation! Different tools in different versions may result differently.

Table 2 Estimated resource Utilization

Tool/Resource	Inputs	Outputs	LUT5	FF	Carry	DSP	BRAM
General	0	1	2	2	0	0	0