Interface

• UART IP Core
  • Authors
  • Revision History
  • Introduction
  • IO ports
  • Registers
  • Operation
  • Architecture
• SPI Core
  • Authors
  • Revision History
  • Introduction
  • IO ports
  • Registers
  • Serial Peripheral Status Register [SPSR]
  • Serial Peripheral Data Register [SPDR]
  • Serial Peripheral Extensions Register [SPER]
  • Operation
  • Architecture
• PWM/Timer/Counter IP Core
  • Authors
  • Revision History
  • Introduction
  • Architecture
  • Operation
  • Registers
  • IO ports
  • Appendix
• I2C-Master Core
  • Author
  • Revision History
  • Introduction
  • IO ports
  • Registers
  • Operation
  • Architecture
  • Programming examples
  • Appendix A
• GPIO IP Core
  • Authors
  • Revision History
  • Introduction
  • Architecture
  • Operation
  • Registers
  • IO ports
  • Appendix
• Wishbone Scope
• Wishbone LCD Controller
• Wishbone LCD Controller RAM-Less
• Wishbone QSPI
• Wishbone RS232 Controller
• Wishbone 1-Wire Master
• Wishbone SPI Master
• Real-time Clock
• RS485 Interface